1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to improvement in a method of driving word lines in a dynamic type MOS-RAM (Metal-Oxide Semiconductor Random Access Memory).
2. Description of the Prior Art
FIG. 1 partially illustrates an exemplary construction of a word line driving part of a conventional dynamic type semiconductor memory device.
Referring to FIG. 1, the word line driving part is formed by a plurality of memory cells 3 arranged in the form of a matrix for storing information, word lines WL.sub.0, WL.sub.1, . . . connected with selection terminals (gate electrodes) of the memory cells 3 arranged in identical rows, bit lines BL and BL connected with data input/output terminals of the memory cells 3 arranged in identical columns and intersecting over the word lines WL.sub.0, WL.sub.1, . . . , a row address decoder 1 for decoding supplied row address signals, word line driving transistors Q.sub.00, Q.sub.10, . . . provided for the respective ones of the word lines WL.sub.0, WL.sub.1, . . . for receiving corresponding decoded address signals from the row address decoder 1 at the gates thereof to be turned on/off to transfer or not to transfer word line driving signals .phi..sub.R to the corresponding word lines WL.sub.0, WL.sub.1, . . . thereby to select the same, transistors Q.sub.01, Q.sub.11, . . . provided for the respective ones of the word lines WL.sub.0, WL.sub.1, . . . to be turned on/off responsive to control signals from a control circuit 10a thereby to prevent erroneous selection of non-selected word lines, transistors Q.sub.02, Q.sub.12, . . . provided for the respective ones of the word lines WL.sub.0, WL.sub.1, . . . to be turned on/off in response to signals RAS for providing timings for introducing the row address signals thereby to hold the respective word lines at low levels in non-active cycles, the control circuit 10a for generating signals RQ for controlling operations of the transistors Q.sub.01, Q.sub.11, . . . , sense amplifiers 2 for respectively sensing data appearing on the respective pair of bit lines BL and BL and restore circuits 4 for further amplifying potential difference appearing on the pairs of bit lines BL and BL after data sensing.
Each of the memory cells 3 is formed by a capacitor for storing information in the form of charges and a selection transistor for reading/writing the information from/in the capacitor. The selection transistor has a gate connected to one of the word lines WL.sub.0, WL.sub.1, . . . , one conduction terminal connected to one of the bit lines BL and BL and another conduction terminal connected to one electrode of the storage capacitor.
Each of the transistors Q.sub.00, Q.sub.10, . . . has a conduction terminal connected to the corresponding one of the word lines WL.sub.0, WL.sub.1, . . . , another conduction terminal receiving the word line driving signal .phi..sub.R and a gate receiving the decoded address signal from the row address decoder 1.
Each of the transistors Q.sub.01, Q.sub.11, . . . has a drain connected to the corresponding one of the word lines WL.sub.0, WL.sub.1, . . . , a source connected with a ground potential and a gate receiving the control signals RQ.
Each of the transistors Q.sub.02, Q.sub.12, . . . has a drain connected to the corresponding one of the word lines WL.sub.0, WL.sub.1, . . . , a source connected with a ground potential and a gate receiving the signals RAS.
The control circuit 10a is formed by n channel MOS transistors Q.sub.1, Q.sub.2 and Q.sub.3. The transistor Q.sub.1 has a source connected to a supply potential V.sub.CC, a gate receiving the signal RAS and a drain connected to an output terminal. The transistor Q.sub.2 has a source and a gate both connected to the supply potential V.sub.CC and a drain connected to the output terminal, to serve as a resistor. The transistor Q.sub.3 has a drain and a gate both connected to the output terminal and a source receiving the signals RAS, to serve as a resistor.
The control signals RQ from the control circuit 10a are delivered, responsive to the signals RAS, to be supplied to the gates of the transistors Q.sub.01, Q.sub.11, . . . . Thus, the respective transistors Q.sub.01, Q.sub.11, . . . are brought into ON states especially upon rise of potentials on the word lines WL.sub.0, WL.sub.1, . . . and in restore operation of memory cell data, to bring the potentials on non-selected word lines into the ground potential level, thereby to prevent erroneous selection of the non-selected word lines.
The term "restore operation" indicates such operation as further amplifying the potential difference after the sense amplifier sensed to amplify a potential difference on a selected pair of bit lines.
FIG. 2 is a diagram showing operation waveforms of the circuit as shown in FIG. 1.
Referring to FIG. 2, the word lines are representatively shown by WL.sub.0 and WL.sub.1, and the bit lines are represented by a pair of bit lines BL and BL.
A signal RAS is an active low row address strobe signal for supplying the timing for introducing a row address signal.
A signal RQ delivered from the control circuit 10a is a clock signal generated synchronously with fall of the signal RAS, to slowly fall to a potential V.sub.T +.alpha. at a time constant determined by the transistors Q.sub.2 and Q.sub.3 forming the control circuit 10a and serving as resistors. Symbol V.sub.T indicates the threshold voltage of the transistor Q.sub.3 and the value .alpha., which is 0.1 to 0.2 V in general, depends on the driving ability of the transistors Q.sub.2 and Q.sub.3.
A signal .phi..sub.R rises in a delay by a predetermined delay time from the fall of the signal RAS to supply a predetermined potential to a selected word line, and the high level of .phi..sub.R is boosted to be higher than V.sub.CC +V.sub.TH in order to completely read and write signal charges. Symbol V.sub.CC indicates the supply potential, and symbol V.sub.TH indicates the threshold voltage of the selection transistor of the memory cell 3 connected to the word line.
With reference to FIGS. 1 and 2, description is now made on data sensing operation in the conventional semiconductor memory device.
At a time t.sub.1, the signal RAS starts falling thereby to start an active cycle for data sensing. Responsive to the fall of the signal RAS, an external address signal is latched by a latch circuit (not shown) and the latched row address signal is supplied to the row address decoder 1. The row address decoder 1 decodes the supplied address signal, to supply a corresponding decoded address signal to the gates of the transistors Q.sub.00, Q.sub.10, . . . . In the control circuit 10a, the transistor Q.sub.1 enters an OFF state responsive to the fall of the signal RAS, and the control signal RQ is restricted by the resistance values of the transistors Q.sub.2 and Q.sub.3, to slowly fall.
At a time t.sub.2, the output potential of the row address decoder 1 is stabilized so that only one decoder output becomes "1" and the other decoder outputs become "0", whereby the word line driving signal .phi..sub.R starts rising to be transferred to the word line WL.sub.0 through the transistor Q.sub.00 selected by the output of the row address decoder 1 to be conductive, and hence the signal level on the selected word line WL.sub.0 starts rising. It is assumed here that the word line WL.sub.0 is selected and the non-selected word line is represented by WL.sub.1, for convenience of illustration.
The signal RQ is outputted from the MOS transistors Q.sub.2 and Q.sub.3 serving as resistors, and slowly falls responsive to rise of the signal RAS as shown in FIG. 2. The signal RQ is supplied to the gates of the transistors Q.sub.01, Q.sub.11, . . . for preventing erroneous selection. Thus, in the case where the word line driving signal .phi..sub.R rises before the non-selected decoder output is stabilized, i.e., before the same is sufficiently brought into a low level, the potential of the non-selected word line WL.sub.1 is prevented from slightly floating up to be erroneously selected.
The word line driving signal .phi..sub.R is transferred onto the word line WL.sub.0 through the transistor Q.sub.00 in an ON state, whereby the potential on the word line WL.sub.0 rises and the word line WL.sub.0 is selected. As the result, the transistor of the memory cell 3 connected to the word line WL.sub.0 enters an ON state, whereby information stored in the memory cell 3 is read out on the bit line BL, followed by potential difference between the bit lines BL and BL.
At a time t.sub.3, the sense amplifier 2 connected with the pair of bit lines BL and BL is activated by an activating means (not shown), whereby the lower-potential one of the pair of bit lines BL and BL is brought into the ground potential level.
At a time t.sub.4, the restore circuit 4 is activated by an activating means (not shown) to perform restore operation, whereby the higher-potential one of the pair of bit lines BL and BL is boosted to the level of the supply potential V.sub.CC. The potential of the signal RQ is (V.sub.T +.alpha.) at this time. Thus, the respective word lines WL.sub.0 and WL.sub.1 are connected to the ground potential through the high-resistance transistors Q.sub.01 and Q.sub.11, whereby the potential of the non-selected word line is prevented from floating up through stray coupling capacitance of the bit lines and the word lines, and hence erroneous selection is prevented.
At a time t.sub.5, the signal RAS rises to complete the active cycle.
In order to completely read and write the signal charges, the word line driving signal .phi..sub.R is boosted to be higher than V.sub.CC +V.sub.TH, as described hereinbefore. Such boosting is generally achieved by supplying the word line with charges precharged at capacitance (such step is not shown). In this case, however, the transistors Q.sub.01, Q.sub.11, . . . are in high-resistance states through the signal RQ, and the word line potentials are lowered by currents weakly flowing from the word lines to the ground potential level through the high-resistance transistors Q.sub.01, Q.sub.11, . . . , and hence the word line potentials cannot be held at sufficiently high levels.
In the aforementioned word line driving circuit of the conventional dynamic type MOS-RAM, currents flow through the erroneous-selection-preventing transistors Q.sub.01, Q.sub.11, . . . to reduce the word line potentials, and hence the selected word lines cannot be held at sufficiently high levels.
U.S. Pat. No. 4,476,548 to T. Matsumoto et al. entitled "Dynamic Type MOS Memory Device" discloses a memory device in which word line pull-down transistors for connecting word line potentials to the ground potential are turned on for a short period of time upon rise of the word line potentials.